1. Field of the Invention
The present invention relates to a method of fabricating a semiconductor device and, in particular, relates to a method of fabricating a semiconductor device having metal wiring.
2. Description of Related Art
Metal wiring in a semiconductor integrated circuit may cause a serious problem of signal delay due to an increase in wiring resistance and an increase in parasitic capacitance between wires following a reduction in wiring pitch. In order to solve this problem, such a technique that uses copper as a wiring material and a low dielectric constant film (low-k film) as an interlayer insulating film has been essential. As this technique, use has been mainly made of the so-called Damascine process wherein trenches and/or contact holes are formed in a low dielectric constant film, a copper film is embedded therein, then planarization is carried out by chemical mechanical polishing (hereinafter referred to as “CMP”). A porous low dielectric constant film with small holes introduced in the film is known as a typical low dielectric constant film.
In a conventional technique, a low dielectric constant film formed on metal wiring of copper or the like is etched by the use of a resist pattern as a mask to thereby expose the surface of the metal wiring. However, there has been a problem that when ashing is carried out using an oxidizing gas such as O2 plasma in an ashing process for removing the resist pattern, a metal oxide film is formed on the exposed metal wiring to cause failure in electrical continuity (e.g. see JP-A-H08-293490).
FIGS. 12 to 15 are sectional views of a semiconductor device for describing a process of etching a low dielectric constant film to thereby form a contact hole on a metal wire by the use of a forming method according to the foregoing conventional technique.
First, as shown in FIG. 12, a first insulating film 2 and a second insulating film 3 are formed on a semiconductor substrate 1, and a first embedded wire 8 composed of a first barrier metal 6a and a first embedded copper film 7a is formed in the second insulating film 3.
Further, a third insulating film 9, a fourth insulating film 10, and a fifth insulating film 11 are stacked in layers on the second insulating film 3 and the first embedded wire 8, and a resist pattern 13 is formed on the fifth insulating film 11.
Then, as shown in FIG. 13, using the resist pattern 13 as a mask, the fifth insulating film 11, the fourth insulating film 10, and the third insulating film 9 are etched to form a contact hole 14 to thereby expose the surface of the first embedded wire 8.
Then, as shown in FIG. 14, the resist pattern 13 (see FIG. 13) is removed by ashing using an oxidizing gas. In this event, a copper oxide (CuO) 7b in the form of a metal oxide film is formed on the surface of the first embedded wire 8 due to the influence of the oxidizing gas.
The copper oxide 7b serves as an insulating film. Thus, if wiring or a plug is formed in the contact hole 14 with the copper oxide 7b remaining, it may cause an increase in resistance of the contact hole or occurrence of wiring failure (e.g. see JP-A-H08-293490).
If cleaning is carried out to remove the copper oxide 7b shown in FIG. 14 for preventing the phenomena, the fourth insulating film 10 is subjected to occurrence of an undercut 14a as shown in FIG. 15, which may cause failure in embedding a metal film to this portion in a later process.
FIGS. 16 to 18 are sectional views of a semiconductor device for describing a fabrication method according to another conventional technique which is adapted to prevent the formation of the copper oxide 7b (see FIG. 14) on the first embedded wire 8 and the formation of the undercut 14a (see FIG. 15).
As shown in FIG. 16, using the resist pattern 13 as a mask, the fifth insulating film 11 and the fourth insulating film 10 are etched to thereby expose the surface of the third insulating film 9.
Then, as shown in FIG. 17, the resist pattern 13 (see FIG. 16) is removed by ashing with an oxidizing gas. Further, as shown in FIG. 18, using the fifth insulating film 11 and the fourth insulating film 10 as a mask, the third insulating film 9 is etched to thereby expose the surface of the first embedded wire 8.
In this event, since the process, shown in FIG. 17, of removing the resist pattern 13 (see FIG. 16) is performed prior to the process, shown in FIG. 18, of exposing the surface of the first embedded wire 8, no copper oxide (CuO) is formed on the surface of the first embedded wire 8 in FIG. 18.
However, as shown in FIG. 18, since the third insulating film 9 is etched by the use of the fifth insulating film 11 and the fourth insulating film 10 as the mask, facets (inclined surfaces) 14b are formed on side surfaces of the fifth insulating film 11 and the fourth insulating film 10. If such facets 14b are formed, the whole width of the contact hole 14 increases to thereby cause a hindrance to fine processing of the contact hole.
As described above, when forming the contact hole on the metal wire of copper or the like, either of the foregoing methods, i.e. the conventional ashing with the oxidizing gas, cannot achieve both the prevention of formation of the metal oxide film on the metal wire and the fine processing of the contact hole.
As described above, there has been a problem that, in the semiconductor device fabrication method which forms the contact hole on the metal wire, either of the foregoing conventional techniques cannot achieve both the prevention of formation of the metal oxide film on the metal wire and the fine processing of the contact hole.
The present invention has been made for solving the foregoing problem and has an object to provide an excellent semiconductor device fabrication method adapted to form a trench or a contact hole on a metal wire, which can achieve both prevention of formation of a metal oxide film on the metal wire and fine processing capable of obtaining an excellent shape of the contact hole.